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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity stepper is
port (
   clk : in std_logic;
   phase : out std_logic_vector (3 downto 0);
   direction    : in std_logic;
   rst :  in std_logic
  
  );
   end stepper;


architecture st of stepper is
signal step_count :std_logic_vector ( 2 downto 0);

begin
      


process (rst,clk)

begin
 if rst = '0' then
     step_count <= "000";
    else
      if clk'event and clk = '1' then
        if direction = '1' then
          step_count <= step_count +1 ;
    elsif  direction = '0' then
    step_count <= step_count -1 ;
         end if;
         end if;
      end if;
 -- end if;
   end process;
       
    process (step_count)
    
      begin
         
     case (  step_count) is                
       when  "000" =>  phase  <= "0001";      -- 0
       when  "001" =>  phase  <= "0011";      -- 1
       when  "010" =>  phase  <= "0010";      -- 2
       when  "011" =>  phase  <= "0110";   -- 3
       when  "100" =>  phase  <= "0100";   -- 4
       when  "101" =>  phase  <= "1100";   -- 5
       when  "110" =>  phase  <= "1000";      -- 6
       when  "111" =>  phase  <= "1001";   -- 7
       when  others => phase  <= "0000"; 
   
       end case;
   
    end process;
end;

 

 

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