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                                                               Ps2 port  
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity ps2 is


 port (kb_ack       : in  std_logic;
       clk          : in  std_logic;
     rst          : in  std_logic;
   kb_clk       : in  std_logic;
   data_kb   : in  std_logic;
   data_out     : inout std_logic_vector (7 downto 0) ;
      data_ready   : out std_logic;
   parity_error : out std_logic;
    asci   : out std_logic_vector (7 downto 0) ;
   display   : out std_logic_vector (7 downto 0)
   ); 
     end ps2;


architecture behavoral  of ps2 is

COMPONENT  kb_conversion

  port (        clk  : in std_logic;
                rd  : in std_logic;
                scan_code : in std_logic_vector (6 downto 0);
                asci    : out std_logic_vector (7 downto 0);
                display : out std_logic_vector (7 downto 0)
        );
   END COMPONENT;

    --- signal declarations ---

 signal  count              : std_logic_vector (3 downto 0) := "0000";
 signal  tmp_data           : std_logic_vector (10 downto 0);
 signal  data_ready_internal: std_logic;
 signal  parity_chk         : std_logic;
 signal  asci_Signal        : std_logic_vector (7 downto 0);
 signal  display_Signal    : std_logic_vector (7 downto 0);
 signal  data_out_signal    : std_logic_vector (7 downto 0);
 signal  scan_code_signal   : std_logic_vector (6 downto 0);

 signal   clk_Signal  : std_logic;
 signal       rd : std_logic :='0';
 signal       fd : std_logic :='0';
 signal       q1 : std_logic :='0';
 signal       q0 : std_logic :='0';
 signal      count_rd : std_logic;
 
   begin

   process ( rst,kb_clk)
     begin
     if (rst = '0')  then                    
          tmp_data  <= "00000000000";
          count <= "0000";
       parity_chk <= '0';
          
             else
                 
               if  ( kb_clk ='0' and kb_clk'Event  ) then
          
              if   (count = "1010" )   then
                   count <= "0000";
                    data_ready_internal <= '1';
          data_out <= tmp_data ( 9 downto 2);
        
                 else   tmp_data (10 downto 0)  <= data_kb & tmp_data (10 downto 1);
                  count <= count + 1;
         parity_chk <= parity_chk xor data_kb;       
                     data_ready_internal <= '0';      
            
         
       
               end if;
               end if;
          end if; 
       end process;

data_out_signal <= data_out ;

  process ( rst,kb_clk)

   begin
          if  (kb_clk'event and kb_clk ='1' and (count = "1011")) then
               parity_error <=  not parity_chk;
             end if;
    end process;


U1 : kb_conversion
  PORT MAP (clk => clk,
            rd => '1',
            scan_code =>scan_code_signal ,
            asci => asci_Signal,
            display => display_Signal);


--process (scan_code_signal,data_out_signal,asci_Signal,data_ready_internal)
-- begin
--if (not (  data_out_signal = x"F0" )) then
    scan_code_signal  <= data_out_signal (6 downto 0);
 asci <= asci_Signal;
  
--  else
 --  asci <= x"00";
--   scan_code_signal <= x"00";
-- end if ;
 
-- end process;
  display <= display_Signal;

 

process ( data_out_signal, clk,rst)

   begin 
  
 --  if (rst = '0' and(  data_out_signal = x"F0" )) then
    if (data_out_signal(7 downto 4) = x"E")  or (data_out_signal(7 downto 4) = x"F")  then
    q0 <= '0';
    q1 <= '0';
  
      elsif (clk'event and clk ='1')then
  q0 <= data_ready_internal;
  q1 <= q0; 
  end if;
  end process ;
   
    rd <= q0 and (not q1);
       fd <= q1 and (not q0);
  
  --  data_ready <= rd;
    --   count_rd <= rd;

 


 process (clk,rst )
  begin
   if (clk'event and clk ='1') then
     if ( rd = '1' ) then
     count_rd  <= not   count_rd ;
    data_ready <= count_rd;
  else
        data_ready <= '0';  
 
  end if ;
  end if;
     
     
    end process;

  

     end;

 

 

 

 

 

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