Article Index

     

    Here is a example  of part of my design I did in VHDL it is takes in a 12 bit number are sends out a three
    channel pwm to a RGB led to create a colour in theory 4096 diffrent colours are possible 

     

     

     

     

     


    Top view of the component

     

     

    top diagram pwm

      


     

    RTL VIEW     

     

     

     


     

     

     Here is a view of real way it is done in the fpga (I wanted the fpga to uses the  SRL ) that saves space the SRL uses a LUT not as a lookup table
    But as a shift register

     

     

     

     

     

     

     

     

     


     

     

    --____________________________________________________________________________
    --
    --    LLLLLLLLLLLLL 
    --   |                   |
    --   |   ARIETECH  |
    --   |                   |              ArieTech                 _\|//_                    
    --    TTTTTTTTTT              Technology            (` 0-0 ')                   
    --______________________________________________ooO-(_)-Ooo___________________
    --
    --
    -- File name    :  C:\arie_clock\led_pwm.vhd
    -- Title        : 
    -- Library      :  WORK
    --              : 
    -- Purpose      : 
    --              :
    -- Created On   : 1/13/2006 9:34:59 AM
    --              :
    -- Comments     :
    --              :
    -- Assumptions  : none
    -- Limitations  : none
    -- Known Errors : none
    -- Developers   :
    --              :
    -- Notes        :
    -- ----------------------------------------------------------------------
    -- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<
    -- ----------------------------------------------------------------------
    -- Copyright 2006 (c)
    --
    --  owns the sole copyright to this software. Under
    -- international copyright laws you (1) may not make a copy of this software
    -- except for the purposes of maintaining a single archive copy, (2) may not
    -- derive works herefrom, (3) may not distribute this work to others. These
    -- rights are provided for information clarification, other restrictions of
    -- rights may apply as well.
    --
    -- This is an unpublished work.
    -- ----------------------------------------------------------------------
    -- >>>>>>>>>>>>>>>>>>>>>>>>>>>>> Warrantee <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
    -- ----------------------------------------------------------------------
    --  MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THE USE OF
    -- THIS SOFTWARE, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO,
    -- THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR
    -- PURPOSE.
    -- ----------------------------------------------------------------------
    -- Revision History :
    -- ----------------------------------------------------------------------
    --   Ver  :| Arie            :| Mod. Date :|    Changes Made:
    --   v1.0  |       :| 1/13/2006 :| Automatically Generated
    -- ----------------------------------------------------------------------


    library ieee;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;
    use ieee.std_logic_1164.all;
     


    entity  led_pwm is

     port (
      color_data     :in std_logic_vector ( 11 downto 0) ;
      pwm_clock        :in std_logic;
      clk            : in std_logic;
       rst            :in std_logic;
      led_pwm_out    :out std_logic_vector (2 downto 0) 
     
     );

     end  led_pwm;

     


      architecture arc_led_pwm of led_pwm is
     
     signal red_pwm_counter   : std_logic_vector(3 downto 0 );
     signal green_pwm_counter : std_logic_vector(3 downto 0 );
     signal blue_pwm_counter  : std_logic_vector(3 downto 0 );
     signal pwm_load_counter  : std_logic_vector(3 downto 0 );
     signal red_pwm_srl       : std_logic_vector(15 downto 0 );
     signal green_pwm_srl     : std_logic_vector(15 downto 0 );
     signal blue_pwm_srl      : std_logic_vector(15 downto 0 );
     signal d_red              : std_logic;
     signal d_green              : std_logic;
     signal d_blue              : std_logic;


          
                   
    begin
     

    process (rst,pwm_clock)
      begin
        if rst  = '0' then
             red_pwm_counter   <= "0000";
         green_pwm_counter <= "0000" ;
          blue_pwm_counter  <= "0000";
         pwm_load_counter  <= "0000";
     
       else if pwm_clock'event and pwm_clock = '1' then


        pwm_load_counter <= pwm_load_counter + 1 mod 16 ;

        if  pwm_load_counter = "0000" then
          
                  red_pwm_counter   <= color_data(11 downto 8);
                  green_pwm_counter <= color_data(7 downto 4);
                 blue_pwm_counter  <= color_data(3 downto 0);
             end if;

             if (red_pwm_counter  > x"0") then
            d_red <= '1';
            red_pwm_counter <= red_pwm_counter -1;
            else
            d_red <= '0';
           
          end if;
                      
                        if (green_pwm_counter  > x"0") then
            d_green <= '1';
            green_pwm_counter <= green_pwm_counter -1;
            else
            d_green <= '0';
           
          end if;
                      
                        if (blue_pwm_counter  > x"0") then
            d_blue <= '1';
            blue_pwm_counter <= blue_pwm_counter -1;
            else
            d_blue <= '0';
           
          end if;
                   end if;
         end if;       
      end process;

    ----  Process to take the  red green blue counters
    ----

    process ( pwm_clock)
    begin
     if ( pwm_clock'event and pwm_clock= '1' ) then
      
         red_pwm_srl <=    red_pwm_srl(14 downto 0) & d_red;
         green_pwm_srl <=  green_pwm_srl(14 downto 0) & d_green;
             blue_pwm_srl <=  blue_pwm_srl(14 downto 0) & d_blue;
          end if;
          end process;
             
        led_pwm_out(0) <= red_pwm_srl(15);
        led_pwm_out(1) <= green_pwm_srl(15);
        led_pwm_out(2) <= blue_pwm_srl(15);

     

     end; 

    Call me on Skype

    My Tweets

    © 2017 Your Company. All Rights Reserved. Designed By ltheme.com

    Please publish modules in offcanvas position.