Article Index

     

     

     

     

     

    library ieee;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;
    use ieee.std_logic_1164.all;
    entity seven_segment  is
    port(
     
     hex_in :in std_logic_vector ( 3  downto 0);
     seven_seg_out        : out  std_logic_vector  (6 downto 0)
     
     );
    end;

     architecture seven_seg_arc of seven_segment is
           

    begin
     
    process (hex_in)
     
      begin
         
     case (  hex_in ) is                                 --abcdefg
       when  "0000" =>  seven_seg_out  <= "0000001";      -- 0
       when  "0001" =>  seven_seg_out  <= "1001111";      -- 1
       when  "0010" =>  seven_seg_out  <= "0010010";      -- 2
       when  "0011" =>  seven_seg_out  <= "0000110";   -- 3
       when  "0100" =>  seven_seg_out  <= "1001100";   -- 4
       when  "0101" =>  seven_seg_out  <= "0100100";   -- 5
       when  "0110" =>  seven_seg_out  <= "0100000";      -- 6
       when  "0111" =>  seven_seg_out  <= "0001111";   -- 7
       when  "1000" =>  seven_seg_out  <= "0000000";   -- 8
       when  "1001" =>  seven_seg_out  <= "0000100";   -- 9
       when  "1010" =>  seven_seg_out  <= "0001000";   -- A
       when  "1011" =>  seven_seg_out  <= "1100000";   -- B
       when  "1100" =>  seven_seg_out  <= "0110001";   -- C
       when  "1101" =>  seven_seg_out  <= "1000010";   -- D
       when  "1110" =>  seven_seg_out  <= "0110000";   -- E
       when  "1111" =>  seven_seg_out  <= "0111000";   -- F
       when  others =>   seven_seg_out <= "0000000"; 

       end case;

    end process;

    end; -- seven_seg_arc
        

     

    Call me on Skype

    My Tweets

    © 2017 Your Company. All Rights Reserved. Designed By ltheme.com

    Please publish modules in offcanvas position.